1. Field of Invention
The present invention relates to a method of manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method of manufacturing a cylindrical-shaped DRAM capacitor that has a larger storage electrode area, and hence has a higher storage capacity.
2. Description of Related Art
As a microprocessor becomes more powerful, the amount of software programs the microprocessor can execute increases correspondingly. Consequently, memories having a high storage capacity are in great demand. FIG. 1 is a circuit diagram showing the memory unit of a DRAM. As shown in FIG. 1, a memory unit is composed of a transfer transistor 10 and a storage capacitor 11. The source terminal of the transfer transistor 10 is connected to a bit line 12. The gate terminal of the transfer transistor 10 is connected to a word line 13. The drain terminal of the transistor 10 is connected to a storage electrode 14, known also as the lower electrode, of a storage electrode 11. The plate electrode 15, known also as the upper electrode or cell plate, is connected to a fixed voltage source. Furthermore, a thin dielectric layer 16 is formed between the storage electrode 14 and the plate electrode 15.
A capacitor is a critical component in DRAM for data storage. If the amount of charges stored in a capacitor is great, the memory is less vulnerable to corruption by external noise signals, such as alpha particles, which particles result in soft errors when data is retrieved. In addition, frequency of refreshes necessary for bringing up the charges in the capacitor can be lowered considerably. There are a few ways to increase the charge storage capacity of a capacitor, including: (1) increasing the dielectric constant of the dielectric layer so that total amount of stored charges per unit surface area of the capacitor increases; (2) reducing the thickness of the dielectric layer--however, there is always a minimum thickness for a given material before quality and reliability deteriorates; and (3) increasing the surface area of the capacitor as much as possible so that total amount of stored charges can increase--however, increasing the surface area of an individual capacitor reduces the overall level of integration of a DRAM.
Conventionally, storage capacity of a DRAM capacitor is increased by a two-dimensional expansion of its storage electrode. This is the so-called planar type of capacitor. However, a planar type of capacitor normally occupies a large substrate area, and hence is unsuitable for fabricating highly integrated circuits. Consequently, three-dimensional types of capacitor such as the stacked type and the trench type have been developed. Even so, simple three-dimensional structures are incapable of providing adequate capacitance currently demanded by DRAMs. Therefore, methods of increasing the electrode area of a capacitor for a given area on a chip are still being sought.
FIGS. 2A through 2F are cross-sectional views showing the progression of manufacturing steps in producing a cylindrical-shaped DRAM capacitor according to a conventional method. First, as shown in FIG. 2A, a MOS device 200 is provided. The MOS device has source/drain regions 201, a field oxide layer 202 and a gate terminal 203. Thereafter, a thin first oxide layer 204 and a thin silicon nitride layer 205 are sequentially formed over the substrate 200. The silicon nitride layer 205 serves as a barrier layer in subsequent etching operation.
Next, as shown in FIG. 2B, photolithographic and etching operations are carried out to pattern the silicon nitride layer 205 and the first oxide layer 204 to form a first contact opening 206. The first contact opening 206 exposes one of the source/drain regions 201. Thereafter, a first polysilicon layer 207 is deposited over the silicon nitride layer 205 to fill the first contact opening 206 completely. Subsequently, the first polysilicon layer 207 is etched back until the first polysilicon layer 207 and the silicon nitride layer 205 are at the same height level as shown in FIG. 2C.
Next, as shown in FIG. 2D, a second oxide layer 208 is formed over the silicon nitride layer 205. For example, chemical vapor deposition is used to form a silicon dioxide layer. Thereafter, photolithographic and etching processes are used to pattern the silicon dioxide layer 208, thereby forming a second opening 209 that exposes the first opening 206. Subsequently, a second polysilicon layer 210 is formed over the surface of the second opening 209 and the second oxide layer 208 so that the second polysilicon layer 210 and the first polysilicon layer 207 are connected. Then, a third oxide layer 211 is formed over the second polysilicon layer 210.
Next, as shown in FIG. 2E, the third oxide layer 211 is etched back to expose the second polysilicon layer 210, and then the second polysilicon layer 210 is also etched back to expose the second oxide layer 208.
Finally, as shown in FIG. 2F, a wet etching method is used to remove the remaining portion of the third oxide layer 211 and the second oxide layer 208 using the silicon nitride layer 205 as an etching barrier layer. Lastly, a dielectric thin film 212 is formed over the second polysilicon layer 210, and then a third polysilicon layer 213 is formed over the dielectric thin film 212 to form a complete cylindrical shaped DRAM capacitor.
At present, conventional methods of increasing DRAM capacitance centers upon improving the surface profile by, for example, producing various undulating features. Although these methods are capable of increasing surface area and hence capacitance a little, the amount of increase is limited and so cannot meet the higher capacitance demanded, especially for miniaturized devices. Moreover, a large number of steps are required before the desired capacitor structure is formed.
In light of the foregoing, there is a need to provide an improved method of forming cylindrical shaped DRAM capacitor.